The present invention generally relates to methods for fabricating flash memory devices and, more particularly, to methods for fabricating flash memory devices with increased memory cell density
In general, a semiconductor memory device is largely classified as volatile memory or non-volatile memory.
Volatile memory includes Random Access Memory (RAM), such as Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). Volatile memory has the property that data can be input and retained while the memory is being powered, but the data becomes volatile and cannot be retained when the memory is not being powered.
With DRAM memory, the transistor is responsible for the switch function and the capacitor is responsible for the data storage function. If power is not supplied, internal data within the DRAM are automatically lost. In addition, the SRAM has the transistor structure of a flip flop type. Data are stored according to the difference between the degree of driving between the transistors. Internal data within SRAM are also automatically lost when the memory is not being powered.
In contrast, non-volatile memory does not lose stored data even when the memory is not being powered has been developed. Examples of non-volatile memory include Programmable Read Only Memory (PROM), Erasable Programmable Read Only Memory (EPROM), and Electrically Erasable Programmable Read Only Memory (EEPROM).
A flash memory device is an advanced type of EEPROM device that can be erased electrically at high speed without being removed from a circuit board. A flash memory device is advantageous in that it has a simple memory cell structure, has low manufacturing cost per memory, and can retain data even when the memory is not being powered.
In general, memory cells of a flash memory device are formed by laminating a tunnel insulating film, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, and a metal gate layer over a semiconductor substrate. The resulting semiconductor laminate is subsequently etched employing a hard mask pattern, thus forming a plurality of memory cell gate patterns and select transistor gate patterns at the same time.
As semiconductor devices become more highly integrated, semiconductor elements must be formed within an increasingly limited area. As a result, the size of a memory cell gate is gradually reduced. However, a problem exists in that using a hard mask formation process for forming memory cells becomes increasingly difficult as the size of memory cells decreases.
One notable difficulty occurs during the formation of memory cells for a flash memory device having a line width of 60 nm or less. Where a photolithography process is performed using ArF exposure having a wavelength of 193 nm, deformation of the memory cell pattern often occurs. As a result, not only must the fabrication process used be capable of producing memory cells meeting existing requirements (formation of an accurate pattern, a vertical profile, and so on), the fabrication process must also avoid producing deformed memory cell patterns.